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UPC2771TB
OUTLINE DIMENSIONS
(Units in mm)
LEAD CONNECTIONS
UPC2771TB
PACKAGE OUTLINE S06
2.1 ± 0.1
(Top View)
(Bottom View)
1.25 ± 0.1
3
4
4
3
2.0 ± 0.2
0.65 3
4
0.2 +0.1
-0
2
5
5
2
1.3
0.65 2
5
1
6
6
1
1
6
DOT ON
1. INPUT
0.9 ± 0.1
0.7
PIN DESCRIPTION
0~0.1
BACK SIDE
+0.1
0.15 -0.5
2. GND
3. GND
4. OUTPUT
5. GND
6. V CC
Pin
No.
Pin
Name
Applied
Voltage
Description
Internal
Equivalent
(V)
Circuit
1
Input
—
Signal input pin. An internal matching circuit, configured
with resistors, enables 50 ? connection over a wide
6
bandwidth. A multi-feedback circuit is designed to cancel
the deviations of h FE and resistance. This pin must be
coupled to the signal source with a blocking capacitor.
4
4
Output
Signal output pin. Connect an inductor between this pin
and VCC to supply current to the internal output transistors.
6
VCC
2.7 to 3.3
Power supply pin. This pin should be externally equipped
1
with a bypass capacitor to minimize ground impedance.
2
GND
0
Ground pins. These pins should be connected to system
ground with minimum inductance. Ground pattern on the
board should be formed as wide as possible. All the ground
pins must be connected together with wide ground pattern
to minimize impedance difference.
3
2
5
ORDERING INFORMATION
PART NUMBER
UPC2771TB-E3
QTY
3K/Reel
Note: Embossed Tape, 8 mm wide. Pins 1, 2 and 3 face perforated
side of tape.
EXCLUSIVE NORTH AMERICAN AGENT FOR
RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS
CALIFORNIA EASTERN LABORATORIES ? Headquarters ? 4590 Patrick Henry Drive ? Santa Clara, CA 95054-1817 ? (408) 988-3500 ? Telex 34-6393 ? FAX (408) 988-0279
24-Hour Fax-On-Demand: 800-390-3232 (U.S. and Canada only) ? Internet: http://WWW.CEL.COM
DATA SUBJECT TO CHANGE WITHOUT NOTICE
PRINTED IN USA ON RECYCLED PAPER -12/97
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